Custom PCB Design for an Edge-AI Project: A Comprehensive Step-by-Step Guide
0) Prerequisites and Key Project Decisions
Before beginning detailed design, define the foundational parameters:
AI Workload Specification: Identify computing requirements including image processing (e.g., via DVP camera), audio input (e.g., PDM microphones), sensor fusion capabilities, etc.
Mechanical Constraints: Establish the physical form factor, including board outline, mounting provisions, and connector placement based on enclosure and integration needs.
Power Budgeting: Determine source options (battery-powered or USB-C 5 V) and calculate peak currents for the AI SoC, radios, sensor arrays, and peripherals under worst-case scenarios.
Assembly Process: Decide between hand-assembly for prototyping or automated pick-and-place for scale, influencing component package selection and stencil design.
Fabrication Constraints: Choose fabrication technology and design rules such as baseline 6/6 mil trace/space with standard vias, or advanced HDI with 3/3 mil trace/space and microvias for high-density layouts.
Recommendation: For rapid prototyping, consider integrating off-the-shelf modules like the Sipeed K210 or ESP32-S3-WROOM before committing to custom chip-down designs, transitioning to chip-down once system requirements stabilize.
1) System Architecture Definition
A clear block-level system perspective aids component selection and interconnection planning:
Core Processing Unit: Kendryte K210 SoC with RISC-V CPU and integrated Neural Processing Unit (NPU) for Edge AI inference acceleration.
Memory: Combine internal SRAM with external QSPI flash for firmware and model storage.
Sensors: Interface a DVP camera module (e.g., OV2640 or OV5640) and dual PDM digital microphones optimized for keyword spotting or wake-word detection.
Connectivity: Integrate Wi-Fi capability via ESP32-C3/S3 modules connected over SPI or UART interfaces.
Power Management: Accept 5 V input from a USB-C connector, stepped down via synchronous buck to 3.3 V and followed by low-noise LDO regulators providing 1.8 V rails.
Debug Interfaces: Include USB-to-UART bridge IC (e.g., CP2102 or CH340), UART headers, and optional JTAG/SWD debugging ports.
2) Power and Thermal Management
Ensuring stable power delivery and effective heat dissipation is critical:
Current Estimation: Sum the maximum currents of the K210 under load, Wi-Fi transmission, camera module, microphones, and indicator LEDs with a safety margin (~30% headroom).
Regulator Selection: Utilize high-efficiency synchronous buck converters for primary 3.3 V rail and low-dropout (LDO) regulators for sensitive 1.8 V analog/digital rails requiring low ripple.
Power Distribution Tree: Design cascaded protection and regulation: USB-C → Overvoltage Protection (OVP) / Electrostatic Discharge (ESD) → Buck converter (3.3 V) → LDO (1.8 V).
Thermal Design: Implement a thermal pad and via array beneath the K210 to channel heat to internal planes and bottom layers; position high-power, high-loss components away from RF radios to minimize noise coupling.
Protection Features: Include input fuses or resettable polymer fuses, transient voltage suppressors (TVS), reverse polarity protection (if appropriate), soft-start circuitry, and power-good (PG) signals chained to system reset for reliable startup sequencing.
3) PCB Stack-up and Design Rules
For controlled impedance and signal integrity, a multi-layer stack-up is recommended:
Layer Configuration:
L1 (Top): High-speed signals and critical components (K210, flash, camera interface).
L2: Solid ground plane.
L3: Signal routing (camera bus, SPI interfaces).
L4: Power planes (3.3 V, isolated 1.8 V domains).
L5: Low-speed signals, GPIO.
L6 (Bottom): Ground and low-speed signals.
Fabrication Guidelines:
Trace and space: 6/6 mil standard; optionally 3/3 mil for HDI designs.
Via sizes: 0.3 mm drill with 0.6 mm pad; microvias optional for HDI.
Impedance control: Target 50 Ω single-ended, 90 Ω differential where applicable.
Solder mask expansion: 3–4 mil expansion to protect pads during assembly.
4) Schematic Capture Best Practices
Design your schematic to reflect system blocks and ensure robust electrical performance:
Power and Ground Networks: Draw a clear power hierarchy including USB-C input, regulators, power-good signals, enable pins, and adequate decoupling.
Core and Clock Circuits: Capture the K210 with proper reset, clock sources, and boot mode configurations.
Memory Interface: Connect QSPI flash matching voltage rails and timing parameters precisely.
Sensory Inputs: Include connectors for DVP camera and PDM mics with appropriate biasing, filtering components, and digital interface lines.
Connectivity and RF: Model ESP32 modules with antenna keep-out zones, external antenna connectors if used, and necessary RF ESD protection.
Debug Interface: Define USB-UART bridge, test points, headers, and status LEDs.
ESD Protection: Protect sensitive I/O and connectors with TVS diodes or dedicated chips.
Decoupling Capacitors: Apply bulk capacitors (10–47 µF) near regulators and local 0.1 µF + 1 µF ceramic capacitors for every power pin group on the K210, placed as close as physically possible to minimize loop inductance.
5) Libraries, Footprints, and Assembly Features
Use verified manufacturer footprints sourced from module vendors or IC datasheets.
Validate paste stencil openings, especially for QFN or BGA packages in chip-down designs, to avoid soldering defects.
Incorporate fiducials: at least two global and one local per board side to assist automated optical inspection and pick-and-place alignment.
6) Component Placement Strategy
Intelligent component placement minimizes signal degradation and eases assembly:
Position K210 centrally with minimal trace length to flash memory and camera connector.
Place regulators, inductors, and power components away from noise-sensitive sensors and analog microphone circuits.
Keep the Wi-Fi antenna area free from copper pours or components (observe antenna keep-out zones).
Arrange test points and debugging headers along one accessible edge to facilitate probing during validation and manufacturing testing.
Respect connector ergonomics for USB-C access and secure mounting hole locations.
7) Routing Guidelines
Adhere to signal integrity and manufacturability principles during routing:
Ensure continuous ground return beneath high-speed traces (e.g., on L1 over ground in L2).
Keep QSPI flash signals short and length-matched per vendor recommendations.
Route DVP camera pixel bus as parallel groups with minimal layer switching.
Minimize clock and data line lengths of PDM microphones and keep them isolated from switching regulators to reduce noise injection.
Use numerous stitched ground vias around board edges and under noisy components like power regulators.
Prioritize power integrity with wide copper pours, star-point grounding from regulators, and appropriate ferrite beads or filtering components on power lines.
Suggested Net Class Widths:
| Signal Type | Trace/Space (mil) | Notes |
|---|---|---|
| High-speed (QSPI, DVP pixel bus) | 6/6 | Length-match critical |
| Regular I/O | 8/8 | General digital signals |
| Power | 40–80 | As wide as possible for low resistance |
8) Design Rule and Integrity Checks
Complete Electrical Rule Check (ERC) and Design Rule Check (DRC) until the design passes without violations.
Perform Power Integrity (PI) checks such as IR drop analysis to verify voltage stability under load.
Conduct Signal Integrity (SI) simulations, if feasible, for critical high-speed traces.
Evaluate thermal hotspots using simulation or estimate based on component placement.
Validate mechanical clearances around USB-C connectors, antenna zones, mounting holes, and keep-outs.
9) Fabrication and Assembly Documentation
Provide your manufacturer with comprehensive, clearly labeled files:
Gerber files (RS-274X format) and drill files for PCB fabrication.
Board outline file with stack-up notes describing layer structure, copper weights, surface finish (ENIG recommended).
Bill of Materials (BOM) listing Manufacturer Part Numbers (MPNs) and approved alternates for supply chain robustness.
Pick-and-place file including XYRS (X, Y coordinates, Rotation, Side) for assembly automation.
Assembly drawings with polarity indicators, keep-out zones, and pertinent notes.
Test plan documentation outlining electrical and functional checks.
Send-to-fab instructions specifying target impedance, surface finish, solder mask and silkscreen colors, IPC class (Class 2 typical).
10) Bring-up and Validation Procedure
Conduct visual and Ohmic checks for solder shorts, opens, and proper IC orientation prior to power application.
Power on the board without ICs (if sockets are used) with current limit to verify stable 3.3 V and 1.8 V rails.
Program bootloader and firmware via the USB-UART bridge; confirm serial console access.
Validate peripheral operation: read flash memory ID, connect and test Wi-Fi functionality, capture and stream test frames from the camera, and verify PDM microphone audio loopback.
Perform AI smoke test by running a minimal inference model (e.g., wake word recognition or a 96×96 image classifier) to confirm NPU functionality.
Conduct a thermal soak test under maximum workload for 30–60 minutes, monitoring temperature hotspots with IR camera or thermocouples.
11) Production Test and Scaling
Design bed-of-nails or pogo-pin test pads to enable automated functional testing and firmware flashing.
Develop automated test scripts measuring power consumption, Wi-Fi MAC address retrieval, camera frame acquisition, microphone RMS level, and AI inference latency.
Track manufacturing yields and feedback design improvements such as increased ground stitching or widened power traces to enhance robustness.
12) Alternative Components and Design Options
Based on project needs, consider alternative architectures:
Processor Core: ESP32-S3 for lighter vision/audio tasks or NVIDIA Jetson Nano/Orin NX for more computationally intensive models.
Sensor Options: Upgrade to MIPI CSI cameras for higher bandwidth image data, requiring stricter layout rules.
Storage Expandability: Include microSD card slots for local data logging.
Power Solutions: Integrate Li-ion battery management and charging circuits for portable applications.
Security Enhancements: Add TPM or ATECC608 chips for hardware-based secure boot and model protection.
Deliverables for Manufacturer
Ensure all critical files and documentation are submitted:
✅ Complete Gerber, drill, and PCB stack-up documentation.
✅ BOM with MPNs and alternate parts.
✅ Pick-and-place data with centroid units.
✅ Assembly drawings with polarity and orientation.
✅ Test and bring-up procedures.
✅ Panelization instructions if applicable, fiducials, and tooling holes.
From Concept to Production with MorePCB
MorePCB offers advanced design-for-manufacturability (DFM) checks, rapid prototyping services including HDI boards, and scalable production with consistent quality. Their expertise supports complex Edge AI designs requiring microvias, fine-pitch components, and optimized stack-ups.
