Chiplet Architecture and Advanced Packaging – What PCB Designers Must Know About CoWoS and EMIB in 2026

The era of the monolithic chip is giving way to the era of the chiplet. As AI accelerators, HPC processors, and high-bandwidth memory systems push beyond the physical limits of single-die design, the semiconductor industry has embraced chiplet architecture — disaggregating complex SoCs into smaller, specialized dies assembled in advanced packages. For PCB designers, this shift is not an abstraction. Chiplet architecture PCB design introduces a new set of board-level engineering challenges that did not exist when large monolithic chips sat in conventional packages. Understanding CoWoS, EMIB, and what they demand from the PCB beneath them is now essential knowledge for engineers working on AI, HPC, networking, and high-performance computing hardware.

What Are Chiplets and Why Do They Change PCB Design?

A chiplet is a small, functionally specialized semiconductor die designed to be combined with other chiplets in a single package to form a complete system. Instead of fabricating an entire processor on one die — which becomes increasingly expensive and yield-limited at advanced process nodes — chiplet architecture allows different functional blocks to be manufactured on the process node best suited to each: compute cores on 3nm, I/O on 7nm, memory controllers on 12nm, and so on.

The chiplets are connected inside the package using one of several advanced packaging technologies. TSMC’s CoWoS places chiplets and HBM memory side by side on a silicon interposer, providing extremely dense, low-latency die-to-die interconnects with micro-bump pitches below 55 μm. Intel’s EMIB embeds small silicon bridges directly in an organic substrate, connecting adjacent dies at high density without requiring a full interposer — reducing cost and thermal expansion mismatch compared to full silicon interposer approaches.

For the PCB engineer, the critical point is this: the package containing the chiplets sits on the PCB, and the PCB must support everything the package needs — power delivery at unprecedented current density, signal integrity for hundreds of high-speed differential pairs, thermal management for multi-hundred-watt packages, and mechanical support for large, heavy, thermally stressed assemblies.

Key PCB Design Challenges for Chiplet Architecture PCB Design

Power Delivery Network Design for Chiplet Packages

Chiplet packages — particularly AI accelerator packages using CoWoS with multiple HBM stacks — consume power at densities that challenge even carefully designed PCB power delivery networks. A large AI training accelerator may draw 700 to 1,000 watts from a single package footprint. The PCB must deliver this current with minimal voltage drop from voltage regulators to package power pins, because chiplet-based designs have tighter core voltage tolerance windows than monolithic chips — often ±2 percent or less.

Effective PDN design for chiplet PCBs uses multiple dedicated power planes for each supply rail, decoupling capacitors placed as close as possible to package power pins, and wide copper pours on internal power layers to minimize plane resistance. The inductance of the power delivery path from board-mounted capacitors to package pins must be minimized — requiring careful stackup planning with power and ground planes on adjacent internal layers, and capacitors physically clustered immediately surrounding the package footprint.

Signal Integrity for High-Speed Package-to-PCB Interfaces

Chiplet packages connect to the PCB through hundreds to thousands of solder balls in a ball grid array. High-speed signals leaving the package — PCIe Gen 5 and Gen 6, 112G and 224G SerDes lanes, CXL interfaces, and HBM control signals — must transition from the package substrate through BGA solder balls into the PCB stackup and route to connectors, memory slots, or other devices without excessive loss, crosstalk, or impedance discontinuity.

Each transition — package ball to PCB pad, via through the PCB, trace to destination — introduces signal degradation managed through controlled impedance design, via stub minimization using back-drilling or blind vias, differential pair length matching, and careful BGA fanout routing in HDI PCB layers. For 112G and 224G SerDes lanes, channel loss budgets are extremely tight — every millimeter of trace, every via, and every connector contributes insertion loss that must be accounted for before layout begins.

HDI PCB Requirements for BGA Fanout

Chiplet packages have ball pitches as fine as 0.8 mm or 1.0 mm for standard BGA connections. Routing signals out from beneath a large BGA with fine pitch requires HDI PCB technology — specifically microvias and laser-drilled blind vias that allow signal routing to escape the BGA field without consuming multiple layers of through-hole vias.

HDI PCB stackups for chiplet system boards typically use 1+N+1 or 2+N+2 microvia structures — one or two layers of laser-drilled blind microvias on each outer surface, connecting to conventional through-hole via layers in the core. Minimum microvia diameters of 0.1 mm and laser-drilled via capture pad diameters of 0.25 mm are typical for advanced chiplet system board HDI designs.

Thermal Management for High-Power Chiplet Packages

The concentrated heat flux from a 700 to 1,000-watt chiplet package presents serious thermal management challenges at the PCB level. The PCB must provide a stable mechanical mounting surface for the heat sink or liquid cooling cold plate, distribute mechanical load evenly across the PCB without causing board warpage that stresses BGA solder joints, and conduct heat away efficiently to prevent localized PCB hotspots exceeding laminate temperature ratings.

Thick copper layers — 2 oz or higher on power planes — improve both electrical and thermal performance under the package footprint. Thermal vias conduct heat from the top surface through the board stack. High-Tg laminate materials rated at 170°C or above prevent glass transition-related softening under the thermal cycling that high-power chiplet system boards experience.

Mechanical Considerations for Large Package Assembly

CoWoS packages for large AI accelerators can reach 100 mm × 100 mm or larger. These large packages have significant mass, and the combination of mass, coefficient of thermal expansion mismatch between the package substrate and PCB laminate, and thermal cycling creates mechanical stress in the BGA solder joint array that can cause fatigue cracking over time. PCB designers must account for BGA solder joint reliability through careful selection of PCB laminate CTE, ENIG surface finish for fine-pitch BGA pads, and solder mask opening geometry. Underfill beneath large BGA packages is increasingly used to distribute mechanical stress across the full ball array and improve long-term reliability.

Choosing the Right PCB Manufacturer for Chiplet System Boards

PCBs supporting chiplet-based systems are among the most technically demanding boards in commercial electronics production. HDI microvia structures, tight impedance tolerances, heavy copper power planes, and large package footprints with fine-pitch BGA fanout all require manufacturing capability well beyond standard PCB production.

• HDI and microvia capability — Chiplet system boards require laser-drilled blind microvias for BGA fanout. MorePCB manufactures HDI PCBs supporting microvia structures for fine-pitch BGA escape routing.
• Multilayer capability and fine trace geometry — Chiplet system boards typically use 12 to 20 copper layers. MorePCB manufactures PCBs from 1 to 50 layers with minimum line and space width of 2.5 mil.
• Thick copper for power delivery — PDN layers for high-power chiplet packages require 2 oz to 4 oz copper. MorePCB supports finished copper weights from 0.5 to 12 oz across all layer types.
• ENIG surface finish — ENIG is the standard surface finish for fine-pitch BGA pads. MorePCB offers ENIG as a standard surface finish option for flat, oxidation-resistant, reliable BGA assembly.
• IPC Class 2 and 3 assembly with X-ray inspection — MorePCB’s assembly operations are ISO 9001:2015 certified with IPC Class 2 and 3 support, full AOI inspection, and X-ray inspection for BGA solder joint verification.
• Global shipping and no minimum order quantity — Chiplet system board development happens at hardware teams worldwide. MorePCB ships to customers in over 60 countries with no minimum order quantity — supporting prototype iterations from a single board through to production volumes. Visit MorePCB for an instant quote, or contact the engineering team at morepcb.com/contact.

FAQ

Q: What is the difference between CoWoS and EMIB for chiplet packaging?

A: CoWoS and EMIB are two leading advanced packaging technologies for integrating multiple chiplets, taking fundamentally different approaches to die-to-die interconnection. CoWoS, developed by TSMC, places chiplets and HBM memory side by side on a large silicon interposer — a thin silicon slab with fine-pitch interconnect wiring — providing extremely dense, uniform, low-latency die-to-die connections across the full package. This makes CoWoS the preferred choice for AI accelerators requiring maximum HBM memory bandwidth. EMIB, developed by Intel, embeds small silicon bridges directly in an organic or glass substrate at specific locations where adjacent dies need high-density connections, eliminating the need for a full silicon interposer. EMIB reduces cost and minimizes coefficient of thermal expansion mismatch compared to full interposer approaches, making it well suited for heterogeneous chiplet designs where dies communicate in pairs rather than requiring full mesh connectivity across all chiplets.

Q: What PCB layer count is typically required for chiplet system boards?

A: Chiplet system boards — particularly those supporting large AI accelerator packages with CoWoS or EMIB technology — typically require 12 to 20 copper layers, with some high-end designs using more. The layer count is driven by several competing requirements: multiple dedicated power planes for the different supply voltages that chiplet packages require, typically 4 to 6 distinct supply rails each needing its own plane; sufficient signal routing layers for the hundreds of high-speed differential pairs exiting the BGA footprint, each requiring controlled impedance with a reference plane immediately adjacent; HDI microvia layers on the outer surfaces for fine-pitch BGA fanout; and ground plane layers interleaved between signal layers to provide return path references and electromagnetic shielding. For standard server or workstation chiplet boards, 12 to 16 layers are typical. For the most complex AI training accelerator boards with multiple chiplet packages and extensive high-speed interconnect, 20 layers or more may be required.

Q: How does HDI PCB technology enable fine-pitch BGA fanout for chiplet packages?

A: HDI PCB technology enables fine-pitch BGA fanout by using laser-drilled blind microvias — vias that connect only two adjacent layers and do not pass through the full board thickness — to route signals from fine-pitch BGA pads on the outer surface down to inner routing layers. A standard through-hole via drilled from top to bottom of a 16-layer PCB occupies a drill diameter of 0.2 mm or more and requires an annular ring on every layer it passes through, consuming significant routing space in the BGA fanout region. A laser-drilled blind microvia connecting only the outer surface to the first inner layer has a typical drill diameter of 0.1 mm and a capture pad of 0.25 mm — far smaller — allowing many more signal escape routes from the dense BGA field. In practice, HDI microvia structures allow every signal ball in a fine-pitch BGA array to have a dedicated escape route to an inner routing layer, which is impossible with through-hole vias alone in arrays denser than 1.0 mm pitch. For chiplet packages with 0.8 mm or finer BGA pitch, HDI is not optional — it is the only manufacturing technology that makes complete signal fanout achievable.

Q: What is UCIe and how does it affect PCB design for chiplet systems?

A: UCIe (Universal Chiplet Interconnect Express) is the industry-standard interface specification for die-to-die communication between chiplets, designed to enable chiplets from different vendors and foundries to interoperate in the same package. UCIe defines the electrical interface, physical bump layout, and protocol layer for chiplet-to-chiplet communication, similar to how PCIe standardized board-level high-speed interconnect. For PCB designers, UCIe matters because it defines the expected I/O behavior of chiplet packages at the package boundary — specifically, what high-speed signals exit the package as BGA balls and need to be routed on the PCB to other devices. UCIe-compliant chiplet packages produce standardized interface signals including PCIe-compatible protocols for host connectivity and CXL for memory-semantic communication — that PCB designers can plan for in their signal integrity budgets and routing strategies. As UCIe adoption grows in 2026, PCB designers working on AI and HPC platforms can expect more predictable chiplet interface electrical specifications, which simplifies high-speed channel planning compared to the proprietary interfaces used in early chiplet designs.

Q: How is power integrity managed for high-current chiplet packages on a PCB?

A: Power integrity management for high-current chiplet packages on a PCB requires a hierarchical decoupling strategy that provides stable supply voltage at each frequency of transient demand. At the lowest frequency — supply regulation bandwidth — the voltage regulator module mounted on the PCB provides the base supply voltage and responds to large, slow load transients over milliseconds. At mid-frequencies — from hundreds of kilohertz to tens of megahertz — bulk capacitors mounted on the PCB surface near the package provide charge reservoir capacity to supply transient current faster than the VRM can respond. At high frequencies — hundreds of megahertz and above — capacitors mounted in the BGA ball field or in the package substrate itself provide the lowest-inductance decoupling for fast chiplet switching transients. The PCB designer’s role in this hierarchy is to minimize the inductance of the path from bulk decoupling capacitors to the package power balls — using dedicated power planes, wide copper pours, and capacitors placed as close as physically possible to the package edge. For the highest-power AI accelerator chiplet packages consuming 700 to 1,000 watts, power plane resistance must be calculated explicitly to verify that IR drop across the PCB power plane does not push core voltage outside the chiplet’s specified tolerance window at full load.

Q: What surface finish is recommended for chiplet package BGA pads on PCBs?

A: ENIG (Electroless Nickel Immersion Gold) is the standard recommended surface finish for BGA pads on PCBs hosting chiplet packages. ENIG provides several properties that make it well suited for fine-pitch BGA assembly. The surface is extremely flat — unlike HASL, which produces uneven solder mounds — which is critical for achieving consistent solder ball height and coplanarity across a large, fine-pitch BGA array. The gold layer prevents oxidation of the underlying nickel surface, providing reliable solderability even after extended storage. The nickel barrier layer prevents copper dissolution into the solder joint during reflow, maintaining consistent joint metallurgy. For the largest chiplet package BGA footprints — 50 mm × 50 mm or larger — pad coplanarity across the entire footprint is particularly important, because any systematic height variation can cause solder bridges on one side and incomplete reflow on the other. ENIG’s consistent, flat surface finish minimizes this risk compared to alternative finishes.

Q: What testing methods verify BGA solder joint quality for chiplet packages?

A: BGA solder joint quality for chiplet packages cannot be verified by automated optical inspection alone, because the solder joints are hidden beneath the package body and invisible to camera-based inspection systems. X-ray inspection is the primary method for BGA solder joint verification, using 2D or 3D X-ray systems to image the solder ball array through the package body. 2D X-ray identifies obvious defects — missing balls, large voids, bridging between adjacent balls — quickly and cost-effectively. 3D computed tomography X-ray provides cross-sectional views that reveal void percentage within individual solder balls, joint height variation, and subtle bridging defects that 2D X-ray misses. For chiplet package assembly on high-reliability system boards, 3D X-ray inspection after reflow is the recommended standard, with void area per joint kept below 25 percent of ball cross-section per IPC-7095 guidelines. Electrical testing — in-circuit test or functional test — provides the final verification that all signal and power connections through the BGA are electrically sound after assembly.

Q: What should I look for in a PCB manufacturer for chiplet system boards?

A: When selecting a PCB manufacturer for chiplet system boards, verify the following capabilities without exception. HDI microvia fabrication — specifically laser-drilled blind microvias at 0.1 mm drill diameter or smaller — for fine-pitch BGA fanout that through-hole via technology cannot achieve. Multilayer capability of at least 16 to 20 layers with tight impedance control across all signal layers, verified by coupon-based electrical testing on every panel. Minimum line and space of 2.5 mil or better for high-density inner-layer routing beneath large BGA footprints. Thick copper support of 2 oz to 4 oz on power planes for high-current AI accelerator PDN design — MorePCB supports 0.5 to 12 oz finished copper weight across all layer types. ENIG surface finish as a standard option for flat, oxidation-resistant BGA pads. High-Tg laminate materials rated at 170°C or above for thermal stability under high-power package operation. ISO 9001:2015 certified IPC Class 2 and 3 assembly with X-ray inspection for BGA solder joint verification. Component sourcing exclusively from authorized distributors to ensure genuine, traceable components for high-value chiplet system builds. No minimum order quantity for prototype iterations — MorePCB accepts single-board orders at any quantity. And global shipping to support chiplet system board development teams wherever they are located. MorePCB ships completed boards and assemblies to customers in over 60 countries worldwide. Get an instant quote at MorePCB or contact the engineering team at morepcb.com/contact.